A complete methodology to analyze discontinuous fiber composites (DFCs)

18
Feb

Discontinuous fiber composites are produced by compressing molding of prepreg chips which are made of unidirectional fiber and thermoset or thermoplastic matrix. Thermoset matrix is consolidated through a chemical/cure reaction at high temperatures, when this curing cycle is not properly monitored, cracks may appear between the chips, caused by the apparition of thermal stresses in the material.

Due to the complex microstructure, these materials required the definition of new methods in order to accurately capture the local orientation and homogenized properties to simulate correctly the design and the curing process.

Hence, the Digimat platform is used to build a complete methodology to compute this problems and to take them into account during the design cycle of the part.

The randomized repartition of the chips is measured experimentally using a CT-scan technology. Using data analysis software, the local orientation tensors are extracted and provide information on how much this orientation varies all over the part. Using Digimat FE to generate DFC like RVE and this orientation tensor for each relevant location, homogenized properties are computed. Mechanical, thermal, shrinkage thermal dependent properties are also computed and then mapped on the mesh used to simulate the curing on the whole part.

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Using Digimat and MSC Marc as a couple, we can simulate the curing process providing accurate results of thermal contraction, cure-shrinkage and residual stress in the structure.

The risk of failure can be evaluated by going back at the RVE level and by applying the temperature and the strain history on the RVE’s boundaries. The crack risk between two chips can be directly connected to the normal stress at the interface of these two chips.

Finally, using Digimat we can propose a complete methodology to analyze DFC, understanding the effects of the microstructure on the behavior of the part, and also, improve the understanding of the effects of the manufacturing cycle parameters evaluating risks for the apparition of defects between chips.

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